1. Field of the Invention
The present invention relates to a clock generator, and more particularly to a clock generator capable of varying its frequency.
2. Description of Related Art
Recently, power saving of semiconductor devices has made a considerable progress. One of the techniques for saving power is to reduce the clock frequency in accordance with the operation mode of a system.
A PLL (Phase Locked Loop) outputs a clock signal synchronized with an input clock signal and having the same or multiplication frequency as the input clock signal. It is essential for recent microprocessors to incorporate the PLL because it can operate at a clock frequency of tens to hundreds megahertz.
FIG. 7 is a block diagram showing a conventional clock generator including such a PLL. Referring to FIG. 7, the clock generator 1000 comprises a PLL 1010 to which an input clock signal is supplied from the outside or inside of the semiconductor device, and a frequency divider 1011 to which the output of the PLL 1010 and a dividing ratio control signal are supplied.
The clock generator further comprises an output buffer 1013 that receives a divided clock signal from the frequency divider 1011 and outputs an external system clock signal; a comparator 1018 that compares the phase of the external system clock signal with that of a feedback clock signal and determines a delay quantity of a DLL (Delay Locked Loop) 1015 in accordance with the compared result; the DLL 1015 that receives the divided clock signal from the frequency divider 1011 and controls its delay quantity in response to the output of the comparator 1018; and an internal circuit 1017 that receives the internal clock signal from the DLL 1015 and a reset signal RST.
The conventional clock generator operates as follows. First, the frequency divider 1011 divides the frequency of the PLL output, and changes the frequency of the divided clock signal by controlling the dividing ratio. The dividing ratio control signal can be supplied directly from the outside of the semiconductor device, or from a circuit on the same substrate operated by the internal clock signal or by a clock signal other than the internal clock signal.
The divided clock signal is translated to the internal clock signal to be supplied to the internal circuit 1017, and to the external system clock signal to be supplied to the outside of the semiconductor device. In this case, it is necessary to match the phase of the external system clock signal with that of the internal clock signal. This is carried out by the DLL 1015 that controls the phase of the external system clock signal and that of the internal clock signal.
FIG. 8 is a circuit diagram showing the frequency divider 1011 of the conventional clock generator 1000. Referring to FIG. 8, the frequency divider 1011 comprises a 1/128 frequency divider 1031a, a 1/64 frequency divider 1031b, . . . , a 1/4 frequency divider 1031f, a 1/2 frequency divider 1031g and a 1/1 frequency divider 1031h, all of which receive the PLL output; a flip-flop 1035 that receives the dividing ratio control signal and a clock signal from the 1/128 frequency divider 1031a; and a multiplexer 1037 for selecting one of the outputs from the 1/128 frequency divider 1031a to 1/1 frequency divider 1031h in response to the output of the D flip-flop 1035.
Smooth switching of the frequency is achieved by setting the delay time of the 1/128 frequency divider 1031a to 1/1 frequency divider 1031h at the same delay time, and by controlling the dividing ratio control signal by the clock signal with the highest dividing ratio (1/128).
FIG. 9 is a timing chart about the conventional clock generator. Referring to FIG. 9, the divided clock signal, internal clock signal and external system clock signal are produced from the frequency divider 1011, DLL 1015 and output buffer 1013 of the clock generator 1000, respectively, by dividing the PLL output. In this case, phase shift can take place between the internal clock signal and external system clock signal when the dividing ratio of the PLL output is changed from two to four, for example.
More specifically, the DLL 1015 can enter a locked state even when the delay time from the output of the divided clock signal to the output of the internal clock signal is shifted exactly one period of the 1/2 clock signal from the delay time from the output of the divided clock signal to the output of external system clock signal. Thus, when changing the dividing ratio from two to four in this state, the internal clock signal will be out of phase after the change as illustrated in FIG. 9, even though it is in-phase before the change.
Therefore, it is necessary for the clock generator 1000 to lock the PLL 1010 or the DLL 1015 again when switching the output frequency of the frequency divider 1011. As a result, such a processing as halting the internal clock signal or resetting the internal circuit 1017 is required to prevent erroneous operation of the internal circuit 1017 when switching the frequency. Thus, the conventional frequency switching is time wasting.
In addition, when the dividing ratio of the clock generator 1000 is low, that is, when it operates at a high speed, the PLL 1010 or DLL 1015 also operates at a high clock frequency by the time it is locked, thereby wasting power.
In summary, the conventional clock generator has a problem of causing phase shift unless the PLL is locked again when switching the frequency. In addition, it has a problem of wasting power when a low dividing ratio is set.
The present invention is implemented to solve the foregoing problems. It is therefore an object of the present invention to provide a power-saving clock generator capable of preventing the phase shift between the clock signals.
According to a first aspect of the present invention, there is provided a clock generator comprising: a frequency divider for outputting a divided clock signal by dividing an input clock signal in accordance with a dividing ratio control signal; an external clock output circuit for generating an external clock signal from the divided clock signal; an internal clock output circuit for generating an internal clock signal from the divided clock signal; and a phase adjusting circuit for adjusting a phase of the internal clock signal with that of the external clock signal, wherein the frequency divider further comprises a dividing ratio control signal inhibiting circuit for disabling the dividing ratio control signal as long as a lock signal supplied from the phase adjusting circuit is active, generates a particular clock signal as long as the dividing ratio control signal is disabled, and changes the frequency of the divided clock signal by enabling the dividing ratio control signal in synchronism with the particular clock signal when the lock signal is made inactive.
Here, the period of the particular clock signal may be greater than a phase adjustable range of the internal clock signal by the phase adjusting circuit.
The particular clock signal may have a longest period in divided clock signals generated by the frequency divider.
The clock generator may further comprise an internal circuit that operates in response to the internal clock signal, wherein the clock generator may maintain a reset state of the internal circuit before the divided clock signal is switched to a desired clock frequency.
The clock generator may further comprise a circuit for halting outputting the internal clock signal before the divided clock signal is switched to a desired clock frequency.
According to a second aspect of the present invention, there is provided a clock generator comprising: a frequency divider for outputting a divided clock signal by dividing an input clock signal in accordance with a dividing ratio control signal; an external clock output circuit for generating an external clock signal from the divided clock signal; an internal clock output circuit for generating an internal clock signal from the divided clock signal; and a phase adjusting circuit for adjusting a phase of the internal clock signal with that of the external clock signal, wherein the frequency divider further comprises a dividing ratio control signal inhibiting circuit for disabling the dividing ratio control signal as long as a control signal takes a first value, generates a particular clock signal as long as the dividing ratio control signal is disabled, and changes the frequency of the divided clock signal by enabling the dividing ratio control signal in synchronism with the particular clock signal when the lock signal is placed at a second value.
Here, the period of the particular clock signal may be greater than a phase adjustable range of the internal clock signal by the phase adjusting circuit.
The particular clock signal may have a longest period in divided clock signals generated by the frequency divider.
Here, the control signal may be placed at the first value at power-on.
The control signal may be placed at the first value at a reset.
The control signal may be placed at the second value after a fixed time interval or after fixed clock cycles after the control signal is placed at the first value.
The control signal may be placed at the second value after the output clock signal is stabilized.
The clock generator may further comprise an internal circuit that operates in response to the internal clock signal, wherein the clock generator may maintain a reset state of the internal circuit before the divided clock signal is switched to a desired clock frequency.
The clock generator may further comprise a circuit for halting outputting the internal clock signal before the divided clock signal is switched to a desired clock frequency.